3D Full Wave Cross-Talk Simulation of Multilayer PCB

The current trend in the silicon industry toward higher levels of integration generates chips with densities of tens of millions of transistors. As a consequence, the signal switching frequency in modem digital equipment is beyond the gigahertz range. When the bandwidth requirement increases, the electrical properties of the interconnects affect and limit the integrity of the traveling digital signals. These phenomena also have an impact on the electromagnetic compatibility (EMC) performance of the system since corrupted signals can easily increase the unwanted electromagnetic interference (EMI).

Until recently, designers performing high-speed PCB simulations were mostly concerned with finding IBIS models for drivers and receivers, but currently the complexity in high speed signals demands additional types of models, not only for IC buffers, but also for packages, vias and connectors. This is a really challenging task, therefore 3D EM field solvers have to be used in order to generate touchstone files or equivalent circuit models to be used in, for example, SPICE-based circuit simulators.

The work presented here was carried out with CST MICROWAVE STUDIO® (CST MWS) and summarises the work by Zianmin Zhang, Kelvin Qiu and Qinghua Bill Chen of Cisco Systems, Inc, presented at DesignCon 2008 [1].

Figure 1 illustrates a complex multilayer (26 layers) PCB imported into CST MWS by using the ODB++ file, which was directly generated from the Cadence® Allegro® *.brd file.

The port assignment is represented in Figure 2, where the main dimensions of the PCB are also highlighted.

Measurements are performed by means of a Vector Network Analyzer (VNA) by using a standard SOLT calibration technique (see Figure 3).

Figure 4 illustrates the comparison between the CST MWS results and the measured results. A very good correlation can be observed for the two considered scattering parameters (cross coupling) over the considered frequency range.

Some discrepancy in the results may be attributed to the measurement set-up. In this case, a micro-probing technique may be more appropriate. A more reliable TRL calibration would allow the length of the cable to be de-embedded as well as the connectors. Figure 5 shows the proposed measurement set-up based on these techniques. This study is planned and will be reported in a future article. Furthermore, the dielectric properties of the material characterizing the PCB were not provided by the manufacturing company and a constant value of dielectric loss was assigned within the considered frequency range.

It has been demonstrated how traditional "rule of thumb" approaches can no longer be used in the Signal Integrity analysis of real high speed PCB structures. This can also easily generate a failure due to inaccuracies, over-simplified modeling, approximation of important physical behaviour etc. The increased complexity of multilayer PCBs, the reduced distance between signal lines, and, at the same time, the increased operating frequency make signal integrity studies (NEXT/FEXT types, eye diagram, TDR as well as S-parameters calculation) with accurate 3D EM field simulators indispensable.

[1]  Antonio Ciccomancini Scogna, Jianmin Zhang, Kelvin Qiu, Qinghua Bill Chen, "Modeling Issues and Possible Solutions in the Design of High Speed Systems with Signals at 20 Gbps," DesignCon, 5-TA3, Feb. 2008.