Signal Integrity of Cadence Allegro® backplane trace import

This article demonstrates the import of traces and associated vias from a Cadence Allegro® backplane file and the consequent  simulations performed in CST MICROWAVE STUDIO® (CST MWS). The import was carried out by selecting a section of the backplane using the 'Export Area' option.  This feature imports the area around the selected differential pair in all 3 dimensions.  The imported structure is displayed in Figure 1 along with a selected view of some of the imported components which include metallic planes, dielectrics and vias.  Four discrete ports are placed on the inputs and outputs of the differential pair, which contains traces dp_p and dp_n. The numbering convention for the ports is: port 1 to 2 for trace dp_p, port 3 to 4 for trace dp_n.

See Figure 2 for the stackup of the 16 layered backplane consisting of 2 external signal layers, 6 internal (stripline) signal layers and 8 ground planes.

A significant signal integrity issue with high speed signals routed in backplanes is the via stub effect.  This effect can be minimized by removing the metal on the signal via. This technique, called back drilling, is commonly used on new backplane designs which need to operate between 3.125Gbs to 6.25Gbs. 

The CST MWS simulation was run using the transient solver over a frequency range of 0-20GHz.  A single simulation is all that is necessary for complete broadband results. The resultant S21 of trace dp_p, which is routed on Layer 3 of the backplane, comparing the through vias to the back drilled vias is shown in Figure 3.  We can clearly see there are significant resonances at 4, 5 and 9 GHz for the through via, which are due to the presence of the large via stub.  On the back drilled via plot there are no resonances present in this frequency range.

CST MWS can generate eye patterns of digital signals.  On Figure 4 is a comparison of the eye patterns for the through and backdrilled signal vias.  The eye pattern for the backdrilled case clearly has more eye opening.

The CST MWS tool can output equivalent circuit models from the S-parameter data.  A Model Order Reduction (MOR) Hspice netlist file which ensures passivity is created for the backdrilled via case.  The resultant S21 of the Hspice model is compared to the S21 of the full wave analysis in Figure 5.  The agreement is relevant over the entire broadband frequency range of 0-20GHz.

In this article the import of a section of a backplane from a Cadence Allegro file into CST MWS  has been demonstrated.  All the metal and dielectric layers are imported and features can be modified within CST MWS.  The CST MWS simulation shows the effect on signal integrity of backdrilling via stubs and an accurate HSPICE model is created. The complete structure was simulated without the need to subdivide it into smaller sections - this is a particular feature of the Time Domain solver which allows complex and large models to be simulated on a standard PC.