CST BOARDCHECK™ is an EMC and SI rule checking program that reads popular board files from Cadence, Mentor Graphics, and Zuken as well as ODB++ (e.g. Altium) files and checks the PCB design against a suite of EMC or SI rules. The kernel used by CST BOARDCHECK is the well known software tool EMSAT.
CST BOARDCHECK’s graphical user interface with EMC rules violation view
The user can designate various nets and components that are critical for EMC, such as I/O nets, power/ground nets, and decoupling capacitors. CST BOARDCHECK relieves the tedium and removes the human error by examining each critical net in turn to check that it does not violate any of the selected EMC or SI design rules. After the rule checking is completed, the EMC rules’ violations can be viewed graphically or as an HTML document.
The world of EMI/EMC compliance has become more important than ever before, due to the higher speed electronics in lower cost packages. The ‘old way’ of best-guess design practice, and then fix the EMI problems after the product is built is not acceptable in today’s market place. Designs must be cost effective, and must pass regulatory requirements the first time through the design cycle.
A typical EMC rules violation view, e.g. for rule Critical Net Crossing Split in Reference Plane
The EMC performance of a printed circuit board is mostly based on the location of the various components and the location of the various critical and I/O nets.
Manual checking of all the layers of today’s high speed circuit boards is too time-consuming and prone to human error. CST BOARDCHECK removes the human error by rigorously analyzing each tagged net and component against the selected rules.