Signal and Power Integrity on PCBs

Printed Circuit Boards (PCBs) are used to mechanically support and electrically connect electronic components using signal traces etched from copper sheets laminated onto non-conductive substrates. The design of PCBs is divided into the following steps: schematics, pre-layout, layout and post layout/verification.

For post layout/analysis and verification, CST MICROWAVE STUDIO® features a powerful EDA import for the translation of any major PCB layout format (such as Cadence, Mentor and Zuken) into a 3D electromagnetic model. EDA specific simulation templates, net selection and automatic port placement are only some of the advanced features which allow the user to easily generate and run the electromagnetic model. A powerful and effective via wizard eases the building of PCB stack-ups in order to study different scenarios and come up with design guidelines for the layout engineer.

The technology partnership between Cadence and CST has resulted in a fully integrated link between Cadence® SiP® and CST STUDIO SUITE® that enables EDA experts to access 3D simulation technologies without ever leaving the Cadence layout environment; model and simulation set-ups as well as back annotation of the results is included.

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Fuji Xerox uses CST STUDIO SUITE for EMC-compliant printer design

Fuji Xerox uses CST STUDIO SUITE for EMC-compliant printer design Document type
Modern multifunction printers include many electronic components – often modular to ensure commonality – and these can interfere with each other causing electromagnetic compatibility (EMC) issues. In addition, electrostatic discharge (ESD) can affect the performance of individual components. Where EMC issues arise during testing, it is not always clear what the cause is. In order to better understand the mechanisms behind these and to find effective mitigation techniques, Fuji Xerox decided to use EM simulation with CST® STUDIO SUITE®. Read full article..

CST STUDIO SUITE Simulations Replace Prototype Builds For Convergentia

CST STUDIO SUITE Simulations Replace Prototype Builds For Convergentia Document type
Portable devices such as smartphones and tablets nowadays contain many wireless systems, including cellular, Wi-Fi and GPS. Each system requires a functional antenna, since poor antenna performance may lead to a bad user experience in the form of low data throughput or poor coverage, and can cause calls to be dropped and car navigation to fail. On the other hand, devices must look appealing and their size must be minimized. The thinness of the devices and the presence of metallic structures have caused challenges to antenna design. Without 3D simulations, there is a high risk of having poor antenna performance or clumsy industrial design. The alternative for antenna verifi cation is to use multiple prototyping rounds, which are expensive and have a long lead time. However, there are things that cannot be effectively studied with prototypes, for example grounding structures and impedance matching networks. Read full article..

Power Delivery Network PDN Analysis

Power Delivery Network PDN Analysis
This webinar consists of two parts. The first part will highlight the role of simulation in the design of PCB power delivery network (PDN) systems, including the voltage regulator module (VRM), decoupling capacitors (decap), and the spreading parasitic of the power/ground plane. The PDN analysis will focus on both the static case (voltage or IR-Drop) and AC analysis in the frequency domain, with the main focus on PDN impedance. In addition to the AC analysis, we will also demonstrate the decap optimizing tool, which is mainly used to optimize the number of decaps while reaching the target impedance. A brief explanation about the SSO (simultaneously switching output) and the major challenges for simulating this (SI/PI co-simulation) will close the first part of this webinar. The second part of the webinar will cover the measurement methodology for the PDN impedance of the power supply plane of the PCB. This will include the measurement the PDN impedance from only one side of the PCB without the connector. Read full article..

3D EM Modeling of a DDR4 Memory Channel

3D EM Modeling of a DDR4 Memory Channel
The modeling section of the webinar will look at the importance of return path discontinuities. When should we use a 2D approach and when do we need 3D full-wave solver? Can we adopt a "cascaded S-parameter” approach to modeling a channel, where each component is simulated separately, or must we revert to "combined 3D modeling", in which the full channel – controller package, motherboard and DIMM connector – are combined in a single 3D CAD model? Read full article..

Simulation for EMC Performance in Modern Electronics

Simulation for EMC Performance in Modern Electronics
The design flow for a modern complex electronic device involves many stages, and the earlier potential EMC problems in the design are detected, the easier and cheaper it can be to mitigate them. In this webinar we will focus on two topics: shielding effectiveness of enclosures and routing of differential lines. Even though the topics sound unrelated, they can be efficiently simulated with the same methods. This webinar uses a realistic demonstrator PCB and enclosure, which were first shown in our webinar from November 2013, “EMC Simulation in the Design Flow of Modern Electronics” – however, this webinar explores different topics and can be watched as a standalone. Read full article..

Dielectric and conductor loss simulation

Dielectric and conductor loss simulation
The drive toward increased integration densities of electronic devices has led to smaller transmission line conductor sizes and structures consisting of multiple lossy dielectrics. At the same time, higher bit-rates of 100 GBits/s, has led to increased loss due to skin-effects. Losses in these types of transmission lines are often difficult to predict due to non-ideal transmission line cross-sections, including surface roughness and edge-shape effects. To develop realistic simulated insertion loss, all insertion loss components need to be considered and accounted for. Dielectric and conductor loss components require careful material parameterization and structure set up. An overview of these parameterizations and set up will be given, including the trace cross-section shape influence on conductor loss, an often overlooked phenomenon. Options for including surface roughness contribution to conductor loss, for both full wave 3D and analytical models, will be explored. Read full article..

High-Speed Serial Link: Full-Wave EM Modeling Methodology and Measurement Correlation

High-Speed Serial Link: Full-Wave EM Modeling Methodology and Measurement Correlation
Passive channels pose significant challenges to serial link transmission for single-ended buses running at very high speeds. With the combined increase in data rates and routing density, crosstalk has become a major source of noise in current PCB designs. Reduced bit-to-bit, bytelane-to-bytelane and channel-to-channel spacing makes timing/voltage active margin analysis more challenging especially for single-ended and bidirectional buses. For this reason simulating a full pad-to-pad link is becoming increasingly desirable. Being able to quickly identify worst case lanes and quantify crosstalk impact is crucial. Such an approach is still very challenging especially for complex systems where the location and nature of aggressor signals change when moving from one component (package, board and connector) to the next. This webinar will cover different aspects of the challenges in high-speed link modeling including chips, packages, PCB’s, connectors and their interactions. A real-world high-speed memory bus test vehicle will be used for the correlation study. Full-wave electromagnetic modeling of the complete 3D link as well as a hybrid 2D/3D link modeling approach will be demonstrated and correlation for both passive (TDR/VNA) and active (system margins) measurements will be presented. The impact on system-level performance is analyzed by comparing results with and without crosstalk from adjacent lanes. Read full article..

eASIC Reduces Multi-Level Package Design Times with CST MICROWAVE STUDIO

eASIC Reduces Multi-Level Package Design Times with CST MICROWAVE STUDIO Document type
eASIC is a fabless semiconductor company specializing in Single Mask Adaptable ASIC™ (application-specific integrated circuits). They produce custom integrated circuits for a wide range of applications, designed with the specific needs of the customers in mind. Supporting customers effectively, especially during the development stage of a new product, requires a rapid, cost-effective design and manufacturing process. Read full article..

CST EMC Flyer

CST EMC Flyer Document type
By law, products must comply with international EMC standards which have been developed to regulate electromagnetic emissions and the susceptibility of electrical and electronic systems. Striking a balance between EMC and competing design requirements poses major challenges to engineers. By including EMC compliant design at an early stage, additional costly development iterations can be avoided later on down the line. Simulation allows problems to be identified and corrected early in the design process, before the first prototype is built. Read full article..

EMC simulation of consumer electronic devices

EMC simulation of consumer electronic devices
All consumer electronic devices need to meet EMC standards. By including EMC compliant design at an early stage, additional costly iterations can be avoided later on down the line. In this webinar we will present how board-level EMC design can significantly reduce emissions at their source. We will then focus on system level EMC, discussing different approaches of segmenting the system for an efficient simulation workflow. Finally we will analyze immunity, by demonstrating how different return current path configurations can affect performance of the device due to cable entry susceptibility. Read full article..

Chip Package Board: Constraint Driven Co Design

Chip Package Board: Constraint Driven Co Design
Memory interfaces have single-ended data rates in the 1GHz-plus range and serial links are running upwards of 10 gigabits per second. A precise analysis of each of these signals is required at silicon, package and board level. The design and optimization performed on each one of these interconnection levels must be done in a global context. This webinar proposes a global methodology which combines three dimensional (3D) electromagnetic (EM) analysis for PCB and package with chip power switching macro-modeling. Difference between segmentation approach (where silicon, package and PCB are analyzed separately and then combined with standard cascading technique) and integrated/global approach (where chip, package and PCB are analyzed as single entity in a co-simulation mode) are discussed and based on the results, guidelines are outlined. Read full article..

Automotive PCBs: Efficient Signal and Power Integrity Analysis

Automotive PCBs: Efficient Signal and Power Integrity Analysis
The increasing demand of in-vehicles infotainment systems, along with active safety and electronic multimedia systems, makes simulation of growing importance in the automotive industry. Building a reliable system, shortening the development cycle and reducing the cost are important factors and the use of simulation tools and virtual prototyping are indispensable to achieve these goals. This webinar presents efficient workflows for signal integrity (SI) and power integrity analysis (PI): the pre-layout is addressed using CST DESIGN STUDIO, and for post layout (both SI and PI) analysis, CST PCB STUDIO® will be employed. Several test models are discussed and guidelines on how to improve existing designs and how to build an optimized system are presented. Read full article..

3D EM simulation of mixed analog / digital multilayer PCB

3D EM simulation of mixed analog / digital multilayer PCB
This article describes the use of CST MICROWAVE STUDIO® (CST MWS) to solve a coupling problem in a mixed analog – digital multilayer PCB card. Courtesy and permission of Alvarion, Ltd, Tel-Aviv, Israel. This example gives an insight into the usefulness of simulation of problems that cannot be investigated easily via measurement and allows the engineer to carry out virtual experiments as demonstrated here with the cutting of the signal trace. Experiments may show the presence of a particular problem but not its location. Even when the problem has been located, further prototypes and experiments are costly and time-consuming. CST MWS offers a straightforward workflow for the set-up and simulation of such problems via its advanced user-interface and EDA interfaces. Read full article..

Analyzing Power Integrity Issues from Power Plane Interactions

Analyzing Power Integrity Issues from Power Plane Interactions Document type
When a printed circuit board (PCB) includes a power plane that is near to signal traces or other power planes, there is a significant risk of energy transfer between parts of the system. Not only does this coupling lead to power switching noise being transferred into data signals, it also means that power supply systems may demonstrate additional resonances that are not seen in the individual components. This can affect the power integrity of the PCB and may reduce its speed or reliability. This paper will explore some of the potential power integrity issues that can affect a PCB and explain how simulation can be used to help reduce these effects. Read full article..

New simulation workflows for predicting radiated emissions

New simulation workflows for predicting radiated emissions
In this video powerful new workflows for reliably predicting radiated emissions from electronics systems will be discussed. We start by importing a complex PCB model into CST PCB STUDIO and applying new EMC rules checking algorithms to rapidly identify potential weaknesses in the design. Critical nets, planes and vias are then analyzed to determine the differential mode (DM) to common mode (CM) conversion caused by driver skew and line imbalance. Finally, the resulting transient noise waveforms are injected into a 3D model of the connector/cable assembly and radiated emissions predicted. Important features of a typical anechoic chamber test are represented in the model using external ground plane reflections and cylindrical scanning to detect the peak emissions. Read full article..

From Layout to Eye Diagram CST STUDIO SUITE and the EDA Workflow

From Layout to Eye Diagram CST STUDIO SUITE and the EDA Workflow Document type
Ensuring good Signal Integrity (SI) in high-speed communication PCBs is becoming more challenging as layouts become more complex, the number of layers increases and the boards get smaller. A full-wave three dimensional (3D) electromagnetic simulator can be used to simulate and visualize the propagation of electromagnetic fields across PCBs. This article will describe how CST STUDIO SUITE® can be successfully used to characterize the response of high-speed channels, and how typical SI results such as S-parameters, Time Domain Reflectometry (TDR) data and eye diagrams can be numerically calculated to predict the response of a channel. The article will also discuss how to modify layouts in order to improve channel performance, and provide some design guidelines. Read full article..

PCB and package codesign and cooptimization

PCB and package codesign and cooptimization
The drive for higher performance leads to increasing complexity and miniaturization of electronic circuit on-chip, more functionality on package level and high density PCB boards. PCB/Package designers are therefore taking the electrical environment via Co-Design and Co-Optimization into account. This webinar addresses the challenges in modeling and simulation for PCB package Co-Design and Co-Optimization. Read full article..

Simplifying the Workflow - benefits of the CST and Cadence Partnership

Simplifying the Workflow - benefits of the CST and Cadence Partnership
Cadence and CST offer very effective solutions for high speed PCB/package co-design. Two different workflows will be presented: 1) the “EDA centric” approach that allows the full wave simulation to be run as a fully background process with back annotation of the results to the layout environment and 2) the “EM centric approach” that focuses on the full wave environment. The benefits of such level of integration in the daily work of design engineers will be discussed. Read full article..

EDA workflow using CST MICROWAVE STUDIO - from Layout to Eye Diagram

EDA workflow using CST MICROWAVE STUDIO - from Layout to Eye Diagram
This webinar will present 3D EM Signal Integrity simulation using CST MICROWAVE STUDIO. It will demonstrate the PCB layout import and the 3D full wave simulation of a realistic multilayer PCB. Standard outputs like S-Parameters, Time Domain Reflection (TDR) and Mode Conversion will be shown along with eye diagram and field distribution. A comparative analysis between time and frequency domain solver will be also presented and trade-offs will be discussed. Read full article..

Electromagnetic Simulation in Radar System Design

Electromagnetic Simulation in Radar System Design
This webcast will discuss the application of CST STUDIO Suite to a full radar system design. CST’s complete simulation technology enables the most appropriate method/solver to be applied to the diverse range of components typically found in a radar system. For the digital design, combined PCB/package analysis is necessary to achieve adequate signal integrity and minimize interference/emissions Read full article..

Electrical Performance of High Speed Signaling in Coupled Microstrip Lines

Electrical Performance of High Speed Signaling in Coupled Microstrip Lines
The electrical performance of high speed signaling in coupled differential microstrip lines is analyzed. Based on the modal decomposition analysis, the cancellation frequency in the single-ended insertion loss response is explained and a closed formula is presented for the prediction of such resonant frequencies. Sensitivity analyses are also performed in order to investigate the impact of the solder mask layer and the differential microstrip geometry on the cancellation frequency. Read full article..

Signal Integrity (SI) analysis with CST PCB STUDIO™

Signal Integrity (SI) analysis with CST PCB STUDIO™
This article highlights the modeling and simulation of signal integrity effects with CST PCB STUDIO™ (CST PCBS). It explains how the technology (layer stackup) can be determined and which modeling options are available. Since SI investigations require significant driver and receiver models, so-called IBIS models are used for the simulation. IBIS is short for I/O Buffer Information Specification and a standard used by many IC manufacturers. Using IBIS models avoids having to creating handmade loads in the schematic and therefore eases the simulation setup process and automatically increases accuracy. Read full article..

3D Full Wave Cross-Talk Simulation of Multilayer PCB

3D Full Wave Cross-Talk Simulation of Multilayer PCB
The actual trend in the silicon industry toward higher levels of integration generates chips with densities of tens of millions of transistors. As a consequence, the signal switching frequency in modem digital equipment is beyond the gigahertz range. When the bandwidth requirement increases, the electrical properties of the interconnections affect and limit the integrity of the traveling digital signals. These phenomena also have an impact on the electromagnetic compatibility (EMC) performance of the system since corrupted signals can easily increase the unwanted electromagnetic interference (EMI). This article summaries the simulations and measurement carried out using CST MICROWAVE STUDIO® on a multilayered PCB. Read full article..

Power Integrity Simulation for High Speed Board using CST PCBS

Power Integrity Simulation for High Speed Board using CST PCBS
Power Integrity simulation for a high speed board, PCI-Express. using CST PCBS is shown here. The first simulation is the static power integrity simulation, known as IR-Drop. The second simulation is the high freq. power integrity simulation, whereas the decoupling capacitors are also taken into account to reduce the impedance of the board. Read full article..

Using CST MWS for Signal Integrity problems

Using CST MWS for Signal Integrity problems
This article is concerned with the important issue of Signal Integrity and the application of CST MICROWAVE STUDIO® to the investigation of the characterisation of an SMA connector on a multi-layer PCB. Read full article..

Visualize, identify and optimize with MWS @ Hirschmann

Visualize, identify and optimize with MWS @ Hirschmann Document type
Winfried Krämer, Hirschmann Automation and Control GmbH Hirschmann Automation and Control is one of the leading providers of industrial Ethernet at bitrates up to 10 Gigabit per second. Using CST MWS we have examined signal paths regarding signal quality, crosstalk and EMC related issues and have identified influences of vias, stackup and other parameters affecting the quality of our high speed interfaces. As the measurement of impedance of critical pins in the power delivery system is challenging, a simulation allows us to evaluate the position dependent information. Furthermore, we also succeeded in improving housing design in RF-matters, tag and optimize the “sites of crime”. Using the capabilities of a simulation helps us to fit the “first shot” layout into a demanding environment and also to optimize an existing layout to ensure performance at growing requirements to the designs. Additionally, it gives us a cost and time effective possibility to answer the “what if” – questions and visualize the points of interest helps to generate reliable constrains. Read full article..

Long Range Connector Via Coupling Effects for High Speed Signals

Long Range Connector Via Coupling Effects for High Speed Signals Document type
Thomas-Michael Winkel, Roland Frech, IBM Entwicklungs GmbH Thomas Gneiting, AdMOS GmbH The interface between a multi pin connector and the printed circuit board is a critical part of the signal path in high speed digital systems like mainframe computers. Long range via coupling effects are analysed for connectors with a huge signal count and high speed signals using CST Microwave Studio simulations. A realistic cross section of the printed circuit board with a mixture of ground and voltage layers have been taken into account. It was possible to understand the reason for this behaviour by analyzing the field distributions during the signal propagation inside the printed circuit board. A further important result was the calculation of the magnitude of the distortions to judge their impact on the signal integrity of a complete system. Finally, the long range crosstalk effect was verified with time domain measurements on a specially designed test card system. Read full article..

Signal Integrity Analysis in Printed Circuit Board and Package Design

Signal Integrity Analysis in Printed Circuit Board and Package Design Document type
Z. Shen, Avago Technologies, Inc. Video of an Innovations 2009 workshop series presentation. Read full article..

Applications of 3D Electromagnetic Modeling in Magnetic Recording: ESD and Signal Integrity

Applications of 3D Electromagnetic Modeling in Magnetic Recording: ESD and Signal Integrity Document type
John Contreras and Al Wallash, Hitachi Global Storage Technologies, presentation at the 5th North American Userforum, 2008. Read full article..

Simulation of vehicle measurement system for radio wave propagation analysis (in Korean)

Simulation of vehicle measurement system for radio wave propagation analysis (in Korean) Document type

Using Full Wave Solvers for Practical Analysis of Capacitor Mounting Structures

Using Full Wave Solvers for Practical Analysis of Capacitor Mounting Structures Document type
Scott McMorrow, Steve Weir, Teraspeed Consulting Group LLC Fabrizio Zanella, CST of America Read full article..

CMOS VCSEL Driver Design using CST MICROWAVE STUDIO® and Agilent ADS

CMOS VCSEL Driver Design using CST MICROWAVE STUDIO® and Agilent ADS
CST MICROWAVE STUDIO® and Agilent ADS have been successfully employed in this OEIC driver design - an example of a high speed analog/broadband IC application.The package model was imported from Agilent momentum and the model was simulated upto a 100 GHz in CST MWS.The resulting eye diagrams of the driver design from CST MWS are compared with those from Agilent momentum and other test cases. Read full article..

EMC Simulation in the Design Flow of Modern Electronics

EMC Simulation in the Design Flow of Modern Electronics
In the design process of modern electronics, every product development starts with a schematic and ends with the physical implementation of the device, typically done in copper. Along the way to converting the schematic into a real existing layout however, the designer can fall into numerous possible pitfalls in terms of the EMC performance. In this webinar we will show several examples of EMC countermeasures in modern electronics and good practices for implementing them, as well as highlighting some common mistakes. We will also demonstrate how simulation can predict the EMC performance of typical components like PCBs, enclosures and cables, and compare the simulation results to measurements performed on physical implementations of the structures. Read full article..

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