CST – Computer Simulation Technology

A Frequency Agile Switched Delay Line Slow-wave BiCMOS Filter

Title:
A Frequency Agile Switched Delay Line Slow-wave BiCMOS Filter
Author(s):
Vishal Bhana, Tinus Stander, Saurabh Sinha
Source:
23rd International Conference Radioelektronika (RADIOELEKTRONIKA), 2013
Vol./Issue/Date:
16 April 2013
Year:
2014
Page(s):
45 - 49
Keywords:
millimeter wave integrated circuits, BiCMOS integrated circuits, Silicon on insulator technology, passive circuits, microstrip filters, integrated circuit modeling
Abstract:
A mm-wave BiCMOS back-end metallization switched delay line frequency agile filter is presented. Miniaturization of the delay lines is achieved by using slow-wave propagation modes on shielded CPWs, with a standard BiCMOS process transistors used as on-chip switching elements. A first-order filter is presented, with simulation results indicating one transmission band at 40.4 GHz of 22.8 % relative bandwidth and insertion loss of –12.25 dB, with the other transmission band at 47.55 GHz with a 23.79 % relative bandwidth and insertion loss of –13.66 dB. Both bands feature below -15 dB input reflection loss. The paper further establishes the potential for shielded CPW transmission lines for the design of complex passive devices on the back-end metallization of various semiconductor technologies.
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