CST – Computer Simulation Technology

Fewest Vias Design for Microstrip Guard Trace by Using Overlying Dielectric
Yung-Shou Cheng, Wei-Da Guo, Guang-Hwa Shiue, Hung-Hsiang Cheng, Chen-Chao Wang, Ruey-Beei Wu
Electrical Performance of Electronic Packaging, 2008 IEEE-EPEP
27-29 Oct. 2008
The unwanted ringing noise owing to the resonance related to the spacing of shorting vias on microstrip guard traces might degrade the signal quality of adjacent interconnects. This paper proposes a novel design method to reduce the ringing noise by overlying a thin dielectric with higher dielectric constant onto the original microstrip substrate. It has the advantages of minimizing the required number ofshorting vias and achieving less restricted circuit routing.

Back to References

contact support

Your session has expired. Redirecting you to the login page...

We use cookie to operate this website, improve its usability, personalize your experience, and track visits. By continuing to use this site, you are consenting to use of cookies. You have the possibility to manage the parameters and choose whether to accept certain cookies while on the site. For more information, please read our updated privacy policy

Cookie Management

When you browse our website, cookies are enabled by default and data may be read or stored locally on your device. You can set your preferences below:

Functional cookies

These cookies enable additional functionality like saving preferences, allowing social interactions and analyzing usage for site optimization.

Advertising cookies

These cookies enable us and third parties to serve ads that are relevant to your interests.