CST – Computer Simulation Technology

Chip/Package/Board: Constraint Driven Co-Design

Recording date: December 6, 2012

60 min

English

 

Memory interfaces have single-ended data rates in the 1GHz-plus range and serial links are running upwards of 10 gigabits per second. A precise analysis of each of these signals is required at silicon, package and board level. The design and optimization performed on each one of these interconnection levels must be done in a global context.

This webinar proposes a global methodology which combines three dimensional (3D) electromagnetic (EM) analysis for PCB and package with chip power switching macro-modeling. Difference between segmentation approach (where silicon, package and PCB are analyzed separately and then combined with standard cascading technique) and integrated/global approach (where chip, package and PCB are analyzed as single entity in a co-simulation mode) are discussed and based on the results, guidelines are outlined.

Watch the Recording

contact support

Your session has expired. Redirecting you to the login page...

We use cookie to operate this website, improve its usability, personalize your experience, and track visits. By continuing to use this site, you are consenting to use of cookies. You have the possibility to manage the parameters and choose whether to accept certain cookies while on the site. For more information, please read our updated privacy policy


Cookie Management

When you browse our website, cookies are enabled by default and data may be read or stored locally on your device. You can set your preferences below:


Functional cookies

These cookies enable additional functionality like saving preferences, allowing social interactions and analyzing usage for site optimization.


Advertising cookies

These cookies enable us and third parties to serve ads that are relevant to your interests.