CST – Computer Simulation Technology

Jitter Compliance of SerDes Channel

USB 3.1 Type C

Recording date: November 15, 2018

60 min



As the data rate keeps increasing for SerDes channels, signal integrity becomes more and more important in the design process. Passive channels with good S-parameters (e.g. low insertion loss) can no longer ensure that the signal has good timing or that it will pass the jitter compliance test. The jitter budget is usually defined at a low bit error rate and it is hard for both simulation and measurement to obtain jitter at this low bit rate.

The Eye Diagram tool in CST Studio Suite® allows engineers to perform jitter analysis efficiently at the very beginning of SerDes channel design as it integrates important techniques for timing analysis (e.g. equalization, encoding and calculation of data independent jitter) in a user friendly GUI. The statistical method used means that jitter at a very low bit error rate can be quickly and accurately estimated.

In this eSeminar, we will present the jitter calculation methodology used in simulations and measurements. By using the example of a UBS 3.1 Type C connector, we will show how to simulate complicated SerDes channels in 3D and perform jitter analysis with the Eye Diagram tool.


Longfei BAI

Longfei Bai is a SIMULIA Solution Consultant supporting customers with EDA. He completed his B.S. at the University of Electronic Science and Technology of China in 2011 and M.S. degrees at the Technische Universität Darmstadt in 2015 in the field of electrotechnics. Bai’s primary focus is now on SI, PI and EMC on PCB, package and chip.


1. Jitter Compliance of SerDes Channel

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