Recording date: October 30, 2014
Moore’s Law states that the number of transistors in an integrated circuit (IC) will approximately double every two years, which means that IC designs are becoming ever denser. As a result, semiconductor industries are now moving to smaller process geometry. This has the additional benefit of helping also to reduce the power consumption as the supply voltage decreases. However, it increases the total current demand, which creates challenges from a power delivery standpoint because of the stringent noise requirement.
This webinar consists of two parts. The first part will highlight the role of simulation in the design of PCB power delivery network (PDN) systems, including the voltage regulator module (VRM), decoupling capacitors (decap), and the spreading parasitic of the power/ground plane. The PDN analysis will focus on both the static case (voltage or IR-Drop) and AC analysis in the frequency domain, with the main focus on PDN impedance.
In addition to the AC analysis, we will also demonstrate the decap optimizing tool, which is mainly used to optimize the number of decaps while reaching the target impedance. A brief explanation about the SSO (simultaneously switching output) and the major challenges for simulating this (SI/PI co-simulation) will close the first part of this webinar. The second part of the webinar will cover the measurement methodology for the PDN impedance of the power supply plane of the PCB. This will include the measurement the PDN impedance from only one side of the PCB without the connector.