Recording date: November 20, 2014
Designing channels for the DDR4 memory architecture is a challenging task due to the wide-band single-ended interface reaching data rates of 3.2GB/s (soon to be extended to 4.266GB/s) per copper lane at a low-voltage of 1.2V. The spectral content can easily reach 15GHz, which means the routing of these signals requires techniques and considerations as they are used in microwave technology. In order to meet tight specifications for cost, power and performance within short design cycles, it is desirable to have a set of modelling guidelines that help to streamline the pre-and post-layout analysis.
In this webinar, we will focus on both design and modeling aspects of the DDR4 memory architecture. While discussing design, we will answer the following questions: What are the acceptable Signal-to-Power and Signal-to-Ground ratios at the controller balls and SDRAM pins? Are we forced to adopt micro- or blind vias? And are we obliged to use high-cost PCB stackups?
The modeling section of the webinar will look at the importance of return path discontinuities. When should we use a 2D approach and when do we need 3D full-wave solver? Can we adopt a "cascaded S-parameter” approach to modeling a channel, where each component is simulated separately, or must we revert to "combined 3D modeling", in which the full channel – controller package, motherboard and DIMM connector – are combined in a single 3D CAD model?