CST – Computer Simulation Technology

Signal Integrity and Power Integrity (SIPI) Day

CST Studio Suite

Join us for an opportunity to learn about the latest developments in 3D electromagnetic simulation in EDA.

Santa Clara Marriott
2700 Mission College Blvd
Santa Clara, CA, 95054 United States
9:00 a.m. - 5:00 p.m.
Date: September 20, 2018
Language: English

Fee: Free of charge
No registration possible.

With the high data rates, compact structure and complex layout of modern circuit boards and packages, maintaining signal integrity (SI), power integrity (PI) and electromagnetic compatibility (EMC) can be difficult. In the competitive electronics market, electromagnetic simulation can offer a decisive advantage, reducing the number of prototypes needed and shortening the design cycle. Join us and learn how CST Studio Suite® can help you ensure strong design in the face of the most challenging problems all within a single easy-to-use interface.

High-speed channel design, simulation of connectors and true signal/power integrity co-extraction and simulation are some of the topics that will be discussed during this symposium. It will feature keynote speeches, in addition to providing an excellent opportunity for engineers to exchange ideas.


  • 9:00 a.m. Registration
  • 9:30 a.m. Welcome and introduction
  • 10:00 a.m. Keynote presentation
  • 10:30 a.m. Connector SI
  • 11:00 a.m. Coffee
  • 11:15 a.m. Keynote: Materials for high speed design
  • 12:00 p.m. Lunch
  • 1:00 p.m. Trends in industry
  • 2:00 p.m. Keynote: SI vs. EMC
  • 2:45 p.m. Coffee
  • 3:00 p.m. Keynote presentation
  • 3:30 p.m. IR drop and decoupling analysis, thermal effects
  • 4:00 p.m. SI/PI co-extraction| IDEMWorks
  • 4:30 p.m. Closing

Registration is required. Lunch and refreshments will be provided.

For more information contact CST or call (508) 665-4400.

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