We briefly explore several approaches to modeling the optoelectronic integrated circuit (OEIC) driver design starting with a purely analog approach with no parasitics or other physical effects. The circuit performance is monitored as more and more physical effects are included. The highest fidelity modeling includes a CST MWS 3D model for the package.
The artwork, substrate layers and metallization layers can be exported from Agilent momentum to CST MWS through a single menu.
The test bench for the driver design was used to simulate various cases (ideal circuit with no parasitics, circuit with multilayer library components, circuit with multilayer components and Agilent momentum solution of the package, circuit with multilayer components and CST MWS solution of the package), all at two different data rates of 1GB/sec and 2.5 GB/sec....
Top-level circuit simulation was performed in Agilent ADS utilizing the S-parameters of the package model exported from CST MWS.
At 1 gigabit per second,the circuit is well-behaved and the eye transitions which include the 3D EM effects are distinct. At 2.5 gigabits per second, once again it is evident that increasing the level of physical effects in the simulation results in greater emphasis of non-idealities in the design.
The inclusion of the CST MWS 3D EM result yields the most accurate representation of the package for this driver design which enables the greatest likelihood of 1st pass design success.