CST – Computer Simulation Technology

Electrical Fast Transient/Burst (EFT/B) Susceptibility of an LV Circuit Breaker

The coupled voltage at component level has been simulated using CST MWS for two PCB releases of the same Low Voltage Circuit Breaker (LV-CB) electronic control scheme. EFT/B was applied to an auxiliary inputs/outputs cable, as in Figure 1. The Low Voltage Circuit breaker (LV-CB) open/close control is performed by means of a digital signal exchange between an ASIC and a micro-controller, each located on two separate boards (horizontal and vertical boards) and linked together with a flexible flat multi-conductor cable. The first PCB release allowed only one GND conductor of the flexible cable between the two boards, while four GND conductors were allowed for the second one.

The assumption was made that a spurious open/close operation occured when noise was added to the digital signals (SER_load signals) and that major coupling between EFT/B and SER_load signals came from common mode coupling between the two separate board GND planes. In such a case, any common mode voltage between the two board GND planes (Umc) is entirely added to the SER_load signals ( Fig.2)....



Figure 1: Simulation focuses on the case (3), where EFT/B is applied to auxiliary inputs/outputs


Figure 2: Equivalent electronic circuit with common mode voltage

Coupled voltage between the two boards is the result of a fully 3D field propagation effect including a complete direct and reverse wave combination between the source and all the connected loads on the PCB. The 3D model, where the electric path between EFT/B to SER_load included EFT/B generator, coupling capacitor, cables, and PCB GND plane, has been entered in CST MICROWAVE STUDIO® (Figure 3). One pulse of the EFT/B time signal was applied at the excitation port (Port 1) and the common mode time signal voltage (Umc) between the two GND planes was recorded.



Figure 3: Equivalent 3D model of the Low Voltage circuit breaker PCB GND plane

The simulated Umc voltage for PCB (a) is plotted in Figure 4. It can be seen that it significantly exceeds the allowed noise margin even for the lowest EFT/B level (2 kV). The SER_load signals are disturbed and a spurious open/close operation occured during EFT/B injection. This result matches well with the experiment.



Figure 4: Simulated PCB (a) Umc voltage

The simulated results of Umc voltage for PCB (b) are plotted in Figure 5. It can be seen that the voltage only touches the allowed noise margin for the highest EFT/B level (3 kV). This result correlates well with experimental results.



Figure 5: Simulated PCB (b) Umc voltage

The time to simulate the Umc voltage in the CST MWS per PCB release was less than 2 hours on a Pentium II 233 MHz, 256 MB RAM.

Rate this Article

contact support

Your session has expired. Redirecting you to the login page...