CST – Computer Simulation Technology

High-Speed Serial Link: Full-Wave EM Modeling Methodology and Measurement Correlation

 

Passive channels pose significant challenges to serial link transmission for single-ended buses running at very high speeds. With the combined increase in data rates and routing density, crosstalk has become a major source of noise in current PCB designs. Reduced bit-to-bit, bytelane-to-bytelane and channel-to-channel spacing makes timing/voltage active margin analysis more challenging especially for single-ended and bidirectional buses. For this reason simulating a full pad-to-pad link is becoming increasingly desirable. Being able to quickly identify worst case lanes and quantify crosstalk impact is crucial. Such an approach is still very challenging especially for complex systems where the location and nature of aggressor signals change when moving from one component (package, board and connector) to the next....

This webinar will cover different aspects of the challenges in high-speed link modeling including chips, packages, PCB’s, connectors and their interactions. A real-world high-speed memory bus test vehicle will be used for the correlation study. Full-wave electromagnetic modeling of the complete 3D link as well as a hybrid 2D/3D link modeling approach will be demonstrated and correlation for both passive (TDR/VNA) and active (system margins) measurements will be presented. The impact on system-level performance is analyzed by comparing results with and without crosstalk from adjacent lanes.

Rate this Video

    Related Videos

  • 3D EM Modeling of a DDR4 Memory Channel

    Designing channels for the DDR4 memory architecture is a challenging task due to the wide-band single-ended interface reaching data rates of 3.2GB/s (soon to be extended to 4.266GB/s) per copper lane at a low-voltage of 1.2V. The spectral content can...

  • High Speed and High Power Connector Design

    As data transfer rates increase and complexity grows, designing high-speed connectors is becoming increasingly challenging, especially with multiple compliance regulations to meet. A precise analysis of the connector in isolation as well as the connector...

  • Power Delivery Network (PDN) Analysis

    This webinar consists of two parts. The first part will highlight the role of simulation in the design of PCB power delivery network (PDN) systems, including the voltage regulator module (VRM), decoupling capacitors (decap), and the spreading parasitic...

  • EMC Simulation of Consumer Electronic Devices

    All consumer electronic devices need to meet EMC standards. By including EMC compliant design at an early stage, additional costly iterations can be avoided later on down the line. In this webinar we will present how board-level EMC design can significantly...

  • PCB and Package Co-Design and Co-Optimization

    The drive for higher performance leads to increasing complexity and miniaturization of electronic circuit on-chip, more functionality on package level and high density PCB boards. PCB/Package designers are therefore taking the electrical environment via...

contact support

Your session has expired. Redirecting you to the login page...