CST – Computer Simulation Technology

Signal Integrity of High Speed Flip Chip Package

Today's flip chip packages contain multiple layers, power and ground planes.  With increasing signal frequencies, signal integrity becomes important at the chip and package levels. CST MWS is used in this example to determine the insertion loss of signals and how it's affected by the ground planes in the package.

There are 11 signal pads and 1 ground pad in the package, as shown in Figure 1.  The ground pad is connected to all the ground planes.



Figure 1: Top view of MWS model

The return currents  for 3 ports are plotted in CST MWS.  Figure 2 shows the port with the largest distance between signal and ground, and therefore the largest return current  on the flip chip structure.



Figure 2: Return current, largest loop

The time domain solver is run at frequencies of 0 to 40GHz.  The variable in the analysis was the number of ground planes in the package.  The insertion loss for the longest net is plotted on Figure 3.  We can see the insertion loss improvement as the number of planes is increased....



Figure 3: Insertion loss, varying number of ground planes

The CST Microwave Studio 3D EM Solver is effectively used to analyze signal integrity in a flip chip package.  The impact of having multiple ground planes in the package is clearly seen by the improvements to the insertion loss.

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