CST – Computer Simulation Technology

Signal Integrity (SI) analysis


This article highlights the modeling and simulation of signal integrity effects with CST PCB STUDIO® (CST PCBS). It explains how the technology (layer stackup) can be determined and which modeling options are available. Since SI investigations require significant driver and receiver models, so-called IBIS models are used for the simulation. IBIS is short for I/O Buffer Information Specification and a standard used by many IC manufacturers. Using IBIS models avoids having to creating handmade loads in the schematic and therefore eases the simulation setup process and automatically increases accuracy.


Board description

The PCB design in this article is a subset of a real world board. The original number of layers is eight but has been reduced to seven for non-disclosure reasons. There is a microcontroller called “IC100” on the left and four memory chips named “IC200”, “IC201”, “IC202”, and “IC203” on the right. The two memory chips “IC202” and “IC203” cannot be seen since they are placed on the bottom side. ...


Figure 1: Subset of a real world PCB design with one microcontroller IC100 (left) and four other ICs (right) two of which are hidden since they are placed on the bottom layer. The highlighted nets are loaded with driver signals and investigated in this article

There are several nets connecting these components, some of them belonging to an address bus and some to a data bus. There is a number of resistor packs (resistor arrays) in the middle of the board that disrupt the direct connection between the five ICs. As an example, net “DATA(0)” connects pin 2 of IC “IC200” and pin 2 of IC “IC2002” with pin 5 of resistor array “R709”. Net “net3983” connects pin 4 on the other side of resistor array “R709” with pin “U20” of IC “IC100”. Figure 2 depicts this by viewing details of the navigation tree in PCBS.


Figure 2: Detail of the navigation tree, showing selected nets “DATA(0)” and “net3983”. These two nets connect the components “IC200”, “IC202” and “R709” on the one side, and “IC100” and “R709” on the other side.

The microcontroller and the four memory chips on the board are products of Freescale and Micron. The corresponding IBIS files “mpc52001.ibs” and “t37z_it.ibs” can be downloaded from the homepages of Freescale and Micron, respectively.


The layer stackup

It is important to determine the board technology before starting modeling and simulation. The reason for this is that parasitic resistances, inductances, capacitances and dielectric losses strongly depend on the materials used, the layer thickness and the distance between the layers. The technology can be defined in the layer stackup manager as shown in figure 3.

Figure 3: The board technology (materials, layer thickness, and distance between signals layers) can be defined in the Layers Stackup dialog. Parameter “fill” decides on in which dielectric (prepreg) the signal lines are embedded.

Net selection

The signal integrity analysis shall be performed for nets “ADDR(5)”, “ADDR(6)”, “ADDR(7)”, “ADDR(8)”, and “ADDR(9)”. A special search function in PCBS ensures that nets “net7695”, “net7696”, “net7697”, “net7698”, and “net7699” on the other side of resistor array “R706” are automatically selected, too. Figure 4 shows the selection highlighted in the PCB design.

Figure 4: Selected nets for the signal integrity analysis are highlighted in white color.

Transmission line modeling

In order to create a simulation model, the board geometry is automatically subdivided into sections with uniform cross-sections. Subsequently a 2D field solver is started to calculate the required line parameters R, L, C, and G. The modeling process is very fast and usually only takes a couple of seconds to minutes.

There is the possibility to view the cross-sections of the individual transmission line systems. As an example, figure 5 shows a typical cross-section in the area between “IC200” and “IC201”. There are seven signal lines located on the third layer from top and embedded between two ground planes. The distance to the ground plane on layer 4 is shorter than the distance to the ground plane on layer 2. It is interesting to note that the seven lines are embedded in the dielectric below as defined in the layer stackup dialog (see parameter “fill” in figure 3).

 CST PCBS allows all other cross-sections of the selected geometry to be viewed as well. This is a convenient way to check the board design in critical areas and to better understand cause and effect of signal integrity issues.


Figure 5: Cross-section of a transmission line system with seven conductors on layer 3. The lines are embedded between a nearby ground plane on layer 4 and a farther ground plane on layer 2. The mutual distance between the lines decides on the strength of cros


Figure 6 shows the schematic for the signal integrity analysis. It consists of a PCB transmission line model block (in the middle), a number of resistors (bottom right) and twenty-two IBIS blocks (left and top right). Two of the IBIS blocks represent driver models (top left) while the remainder are pure receiver models. There are 25 IC pins in the system and 10 resistor pins.

Figure 6: Simulation setup for the signal integrity analysis between microcontroller “IC100” and memory chips “IC200”, “IC201”, “IC202”, and “IC203”. The two IBIS blocks on the top left represent (active) driver models; all other IBIS blocks are receiver model

The simulation is performed in time domain (transient analysis) from 0 ns to 80 ns. Pulse width of the trigger signal is 10 ns and pulse period is 20 ns. The signal at pin “C20” of “IC100” was defined with a delay of 10 ns. Rise and fall times need not to be specified since automatically gained by the used IBIS models. Seven probes in the system were defined in order to monitor ´the signals at the inputs (“IC100”, pins “C19” and “C20”) and the outputs (“IC201”, pins “36”, “37”, “38”, “39”, and “40”).


First simulation results

Figure 7 shows all input and output signals. A signal overshoot can be seen in the rising edges and a dominant undershoot in the falling edges.

Figure 7: Input and output signals at voltage monitors. The overshoots and especially the undershoots are not acceptable. Certain improvements in the loads or the board technology have to be done in order to guarantee signal integrity.

A more detailed view can be seen in figure 8. It is interesting to note that the crosstalk of input signal at “IC100-C19” (red curve) to “IC201-38” (orange curve) is nearly zero although signal “V_IC100_C19” is high. At about 10 ns to 11 ns the signal “V_IC201_38” suddenly increases slightly. The reason is that – now, after a delay time of 10 ns – the input signal at “IC100-C20” becomes active: since the corresponding net is in a closer distance to the victim line, the crosstalk is noticeable.

Figure 8: Detailed view of the input voltage at “IC100-C19” (red line) and output voltage at “IC201-36” (blue line). The orange line (signal at pin “38” of “IC201”) increases after 10ns to 11 ns due to the fact that now the input signal at “IC100-C20” becomes

Improvement of signal integrity

The goal of SI analysis is to improve the quality of the signals at the receivers’ pins and to attenuate crosstalk effects to a minimum. With simulation software this can be easily achieved since changes in both the PCB design and schematic are quickly done. Figure 9 shows the result after certain changes have been made in the schematic. The signals are not perfect yet but the signal undershoots could be noticeably reduced.

Figure 9: to certain changes in the schematic the signal undershoots could be noticeably reduced.


Signal integrity investigations are easily possible with CST PCBS. Common PCB layout formats can be imported by a single mouse-click from Altium, Cadence, Mentor Graphics, or Zuken. Fast and accurate field solvers calculate parasitic electromagnetic effects such as coupling inductances or capacitances and allow investigations into crosstalk effects. Driver and receiver models for the active components on the board can be obtained by using IBIS models. What-if-analyses can be quickly performed in order to find the optimum for signal integrity.

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