AbstractThis article highlights the modeling and simulation of signal integrity effects with CST PCB STUDIO™ (CST PCBS). It explains how the technology (layer stackup) can be determined and which modeling options are available. Since SI investigations require significant driver and receiver models, so-called IBIS models are used for the simulation. IBIS is short for I/O Buffer Information Specification and a standard used by many IC manufacturers. Using IBIS models avoids having to creating handmade loads in the schematic and therefore eases the simulation setup process and automatically increases accuracy.
Board descriptionThe PCB design in this article is a subset of a real world board. The original number of layers is eight but has been reduced to seven for non-disclosure reasons. There is a microcontroller called “IC100” on the left and four memory chips named “IC200”, “IC201”, “IC202”, and “IC203” on the right. The two memory chips “IC202” and “IC203” cannot be seen since they are placed on the bottom side. ...
The layer stackupIt is important to determine the board technology before starting modeling and simulation. The reason for this is that parasitic resistances, inductances, capacitances and dielectric losses strongly depend on the materials used, the layer thickness and the distance between the layers. The technology can be defined in the layer stackup manager as shown in figure 3.
The signal integrity analysis shall be performed for nets “ADDR(5)”, “ADDR(6)”, “ADDR(7)”, “ADDR(8)”, and “ADDR(9)”. A special search function in PCBS ensures that nets “net7695”, “net7696”, “net7697”, “net7698”, and “net7699” on the other side of resistor array “R706” are automatically selected, too. Figure 4 shows the selection highlighted in the PCB design.
Transmission line modeling
In order to create a simulation model, the board geometry is automatically subdivided into sections with uniform cross-sections. Subsequently a 2D field solver is started to calculate the required line parameters R, L, C, and G. The modeling process is very fast and usually only takes a couple of seconds to minutes.
There is the possibility to view the cross-sections of the individual transmission line systems. As an example, figure 5 shows a typical cross-section in the area between “IC200” and “IC201”. There are seven signal lines located on the third layer from top and embedded between two ground planes. The distance to the ground plane on layer 4 is shorter than the distance to the ground plane on layer 2. It is interesting to note that the seven lines are embedded in the dielectric below as defined in the layer stackup dialog (see parameter “fill” in figure 3).
CST PCB STUDIO™ allows all other cross-sections of the selected geometry to be viewed as well. This is a convenient way to check the board design in critical areas and to better understand cause and effect of signal integrity issues.
SimulationFigure 6 shows the schematic for the signal integrity analysis. It consists of a PCB transmission line model block (in the middle), a number of resistors (bottom right) and twenty-two IBIS blocks (left and top right). Two of the IBIS blocks represent driver models (top left) while the remainder are pure receiver models. There are 25 IC pins in the system and 10 resistor pins.
First simulation resultsFigure 7 shows all input and output signals. A signal overshoot can be seen in the rising edges and a dominant undershoot in the falling edges.
Improvement of signal integrityThe goal of SI analysis is to improve the quality of the signals at the receivers’ pins and to attenuate crosstalk effects to a minimum. With simulation software this can be easily achieved since changes in both the PCB design and schematic are quickly done. Figure 9 shows the result after certain changes have been made in the schematic. The signals are not perfect yet but the signal undershoots could be noticeably reduced.
SummarySignal integrity investigations are easily possible with CST PCB STUDIO™. Common PCB layout formats can be imported by a single mouse-click from Altium, Cadence, Mentor Graphics, or Zuken. Fast and accurate field solvers calculate parasitic electromagnetic effects such as coupling inductances or capacitances and allow investigations into crosstalk effects. Driver and receiver models for the active components on the board can be obtained by using IBIS models. What-if-analyses can be quickly performed in order to find the optimum for signal integrity.