CST – Computer Simulation Technology

True Signal / Power Integrity Co-Extraction and Simulation

In this webinar we will present a novel workflow that starts from a Package and PCB layout and yields a high fidelity circuit simulation with signal integrity and power integrity being considered concurrently in the same model. We will give guidelines on what material models should to be used and how to extract an equivalent circuit model that is reliable from DC up to multiple GHz. We will develop these guidelines on a test vehicle before applying them to a real-world model of a DDR4 memory channel that is represented by a 3D model of the Package as well as the system board. As our workflow supports both IBIS and transistor level simulation flows, it is useful to both chip designers as well as system integrators.

Providing a clean power supply voltage is a crucial element of PCB and Package layout design. For the channel, however, often approximations are made as models for the power delivery network (PDN) and the signal nets are extracted separately. This separate extraction neglects the effects of coupling between the power-, ground- and signal nets. We therefore propose a more rigorous approach where only a single model for the channel is extracted that includes both the signal nets as well as the PDN, therefore allowing a SI/PI co-simulation with unprecedented accuracy....

Because problems with reference planes are notoriously difficult to be considered in conventional 2.5D simulations, we will use a full 3D electromagnetic simulation of a test board and package to compute the S-Parameters of the channel, which includes the signal nets as well as the power and ground nets. IdEM, a premium macro-model extraction tool, will generate an equivalent circuit model that can be used in a circuit simulation. As the circuit model will carry both the DC component of the power supply as well as the high frequency signal and high frequency noises, we will have to establish a workflow that ensures accurate performance of the model at very low as well as high frequencies. This poses challenges regarding the material modelling, frequency sampling, as well as SPICE model extraction.

Rate this Video

    Related Videos

  • Design and Characterization of SerDes Channels

    This webinar will highlight the key features for SerDes Channel Design in CST STUDIO SUITE including the new eye diagram tool, demonstrating realistic transmitter and receiver models including jitter, modulation and equalization at both the pre-layout...

  • Precise Characterization of Multipin Connectors

    This webinar will present a technique for the extraction of the connector model from measured S-parameters mitigating the effects of the test-fixture using CST STUDIO SUITE®. The concept will be demonstrated using the example of a connector for automotive...

  • Simplifying the Workflow - Benefits of the CST and Cadence Partnership

    This webcast in the series discusses recent advances in modeling ESD generators using CST STUDIO. Direct transient analysis is used to simulate the ESD test waveforms defined by the IEC 61000-4-2 standard. We demonstrate the importance of modeling the...

  • 3D EM Modeling of a DDR4 Memory Channel

    Designing channels for the DDR4 memory architecture is a challenging task due to the wide-band single-ended interface reaching data rates of 3.2GB/s (soon to be extended to 4.266GB/s) per copper lane at a low-voltage of 1.2V. The spectral content can...

  • Coreless Packaging Technology for Compact, High-Performance Mobile Devices

    The high performance application processors found in today's mobile electronic devices such as smart phones and tablet computers require miniaturized IC packages that can satisfy the demands for compact, low-profile and lightweight products while meeting...

contact support

Your session has expired. Redirecting you to the login page...