The operating frequency of high-speed copper backplane serial links is expected to reach 10 Gbps in the next few years. At a 10 Gbps data rate, the clock frequency is 5 GHz, equating to a period of 200 ps, which results in a signal rise time in the range of 30 to 50 ps. This rise time will influence the analog bandwidth and the highest significant frequency component both for the measurement bandwidth and the bandwidth of the channel model. To effectively design a serial link (channel) to operate effectively at this bandwidth, accurate signal integrity modeling is required.
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